GATE Computer Organization and Architecture previous year questions

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List I: P. Immediate; Q. Indirect; R. Base with index; S. Base with offset/displacement. List II: 1. Element of an array; 2. Pointer; 3. Element of a record; 4. Constant.

1. (A)P-4, Q-3, R-1, S-2
2. (B)P-4, Q-2, R-1, S-3
3. (C)P-1, Q-4, R-3, S-2
4. (D)P-2, Q-3, R-1, S-4

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y ? Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

1. (A)ADD Z, X, Y
2. (B)LOAD R0, X; ADD Z, R0, Y
3. (C)ADD R0, X, Y; STORE Z, R0
4. (D)LOAD R0, X; LOAD R1, Y; ADD R2, R0, R1; STORE Z, R2

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

1. (A)Read-after-read
2. (B)Read-after-write
3. (C)Write-after-read
4. (D)Write-after-write

The size of the physical address space of a processor is 2³² bytes. The capacity of a cache memory unit is 2²³ bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a K-way set-associative cache, where K = 2^L and L ∈ {1, 2, 3}. Let the length of the TAG field be M bits for the direct mapped cache, and N bits for the set-associative cache. Which one of the following options is true?

1. (A)N = M + L
2. (B)N = M - L
3. (C)N = M + K
4. (D)N = M - K

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid. For a given memory reference, which of the following sequences of events can NEVER happen?

1. (A)TLB miss, Page table hit, Cache hit
2. (B)TLB hit, Page table miss, Cache hit
3. (C)TLB miss, Page table miss, Cache hit
4. (D)TLB miss, Page table miss, Cache miss

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let t_EX denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of t_EX and M (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below. The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. Instruction t_EX (ns) M LOAD 1.8 15 IMUL 1.5 10 IDIV 2.5 5 FADD 1.7 10 FSUB 1.7 5 FMUL 2.8 15 FDIV 3.2 5 All other Less than 1.0 35 When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)

Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt. Which one of the following options is correct with respect to S1 and S2?

1. (A)Both S1 and S2 are true
2. (B)Both S1 and S2 are false
3. (C)S1 is true and S2 is false
4. (D)S1 is false and S2 is true

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

1. (A)8
2. (B)4
3. (C)64
4. (D)16

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S, ... Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word = 1 byte). P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32 Which of the following statements is/are true? Note: 1K = 2¹⁰ and 1M = 2²⁰

1. (A)Every access to P results in a cache miss
2. (B)Every access to R results in a cache hit
3. (C)Every access to Q results in a cache miss
4. (D)Except the first access to S, all subsequent accesses to S result in cache hits

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 176 (decimal). The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer) Note: 1K = 2¹⁰ and 1M = 2²⁰

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places) Note: 1G = 10⁹

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives: (i) The processor saves the content of the program counter. (ii) The program counter is loaded with the start address of the ISR. (iii) The processor finishes the present instruction. Which ONE of the following is the CORRECT sequence of steps?

1. (A)(iii), (i), (ii)
2. (B)(i), (iii), (ii)
3. (C)(i), (ii), (iii)
4. (D)(iii), (ii), (i)

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown? Data path (from the figure): Mux_A selects between register RA and a 32-bit immediate value (control: Select RA/immediate). Mux_B selects between register RB and a 32-bit immediate value (control: Select RB/immediate). The outputs of Mux_A and Mux_B are the two ALU inputs (ALU control lines select the operation), and the ALU output is written to RZ.

1. (A)The data path can implement arithmetic operations involving two registers.
2. (B)The data path can implement arithmetic operations involving one register and one immediate value.
3. (C)The data path can implement arithmetic operations involving two immediate values.
4. (D)The data path can only implement arithmetic operations involving one register and one immediate value.

Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K = 2¹⁰, 1M = 2²⁰.]

1. (A)6 × 2¹⁰
2. (B)8 × 2¹⁰
3. (C)2¹²
4. (D)2¹⁴

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction? ADD R1, #25 // R1 = R1 + 25

1. (A)16
2. (B)20
3. (C)22
4. (D)24

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ________. (rounded off to two decimal places) Figure data: L1 cache: hit rate = 95%, access time = 10 ns L2 cache: hit rate = 85%, access time (including L1 cache miss penalty) = 20 ns Main memory: access time (including L1 and L2 cache miss penalty) = 200 ns

Which of the following is/are part of an Instruction Set Architecture of a processor?

1. (A)The size of the cache memory
2. (B)The clock frequency of the processor
3. (C)The number of cache memory levels
4. (D)The total number of registers

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block. Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?

1. (A)64 KB and 4 KB
2. (B)128 KB and 16 KB
3. (C)64 KB and 8 KB
4. (D)128 KB and 6 KB

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the "hit rate" is 80% and the "miss penalty" for transferring data from L2 cache to L1 cache is 10 ns. The "miss penalty" for the data to be transferred from main memory to L2 cache is 100 ns. Then the average memory access time in this system in nanoseconds is ___________ . (rounded off to one decimal place) A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds.

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________. (rounded off to two decimal places)

An application executes 6.4 × 10⁸ number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is _________. (rounded off to one decimal place) Instruction type CPI Number of instructions executed Branch 2 2.25 × 10⁸ Load 5 1.20 × 10⁸ Store 4 1.65 × 10⁸ Arithmetic 3 1.30 × 10⁸

Which one of the following statements is FALSE?

1. (A)In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
2. (B)For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
3. (C)Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
4. (D)The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

1. (A)In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction
2. (B)In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction
3. (C)Forwarding cannot prevent all pipeline stalls
4. (D)Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

1. (A)A read miss in WBC never evicts a dirty block
2. (B)A read miss in WTC never triggers a write back operation of a cache block to main memory
3. (C)A write hit in WBC can modify the value of the dirty bit of a cache block
4. (D)A write miss in WTC always writes the victim cache block to main memory before loading the missed block to the cache

The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be fully parallelized. The overhead for using an additional core is 10 ns when running on a multicore system. Assume that all cores in the multicore system run their share of the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is ________

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is _________

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

1. (A)2,56,000
2. (B)3,200
3. (C)25,60,000
4. (D)32,000

An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be executed in a pipelined processor: I1: DIV R3, R1, R2 I2: SUB R5, R3, R4 I3: ADD R3, R5, R6 I4: MUL R7, R3, R8 Which of the following statements is/are TRUE?

1. (A)There is a RAW dependency on R3 between I1 and I2
2. (B)There is a WAR dependency on R3 between I1 and I3
3. (C)There is a RAW dependency on R3 between I2 and I3
4. (D)There is a WAW dependency on R3 between I3 and I4

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is _________

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. R-type Instruction Format: OPCODE | UNUSED | DST Register | SRC Register 1 | SRC Register 2 I-type Instruction Format: OPCODE | DST Register | SRC Register | # Immediate value/address In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size. Let X be the number of bits used to encode the UNUSED field, Y be the number of bits used to encode the OPCODE field, and Z be the number of bits used to encode the immediate value/address field. The value of X + 2Y + Z is ________

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The total execution time for executing 100 instructions on this processor is ns.

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 μs (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 μs to process the keystroke. Let T1 denote the fraction of a second spent in polling and processing a keystroke. In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let T2 denote the fraction of a second spent in servicing the interrupt and processing a keystroke. The ratio T1/T2 is ________. (Rounded off to one decimal place)

Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

//C-code
int a[10], b[10], i;
// int is 32-bit
for (i=0; i<10;i++)
    a[i] = b[i] * 8;

;assembly-code (; indicates comments)
;r1-r5 are 32-bit integer registers
;initialize r1=0, r2=10
;initialize r3, r4 with base address of a, b
L01: jeq r1, r2, end   ;if(r1==r2) goto end
L02: lw  r5, 0(r4)     ;r5 <- Memory[r4+0]
L03: shl r5, r5, U1    ;r5 <- r5 << U1
L04: sw  r5, 0(r3)     ;Memory[r3+0] <- r5
L05: add r3, r3, U2    ;r3 <- r3+U2
L06: add r4, r4, U3
L07: add r1, r1, 1
L08: jmp U4            ;goto U4
L09: end

1. (A)(8, 4, 1, L02)
2. (B)(3, 4, 4, L01)
3. (C)(8, 1, 1, L02)
4. (D)(3, 1, 1, L01)

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks X1, X2, X3, X4. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a 2-to-4 decoder: IA4 drives decoder input A1, IA3 drives A0, and decoder outputs Q0, Q1, Q2, Q3 drive the CS of X1, X2, X3, X4 respectively. The remaining ten input address lines IA11-IA5 and IA2-IA0 are connected (as a 10-bit bus, IA11 as MSB and IA0 as LSB) to the address port of each block. The chip select (CS) is active high. The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block are among the options given below. Which one of the following options is CORRECT?

1. (A)(0, 1, 2, 3)
2. (B)(0, 1024, 2048, 3072)
3. (C)(0, 8, 16, 24)
4. (D)(0, 0, 0, 0)

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET. The number of bits in the TAG is .

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

1. (A)DMA based I/O transfer
2. (B)Interrupt driven I/O transfer
3. (C)Polling based I/O transfer
4. (D)Programmed I/O transfer

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

1. (A)Each cache block in WB and WT has a dirty bit.
2. (B)Every write hit in WB leads to a data transfer from cache to main memory.
3. (C)Eviction of a block from WT will not lead to data transfer from cache to main memory.
4. (D)A read miss in WB will never lead to eviction of a dirty block from WB.

A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _____________.

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

1. (A)Every access to S is a hit.
2. (B)Once P is brought to the cache it is never evicted.
3. (C)At the end of the execution only R and S reside in the cache.
4. (D)Every access to R evicts Q from the cache.

A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is____________.

Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?

1. (A)I and II only
2. (B)II and III only
3. (C)I and III only
4. (D)I, II and III

The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?

1. (A)QPTRS
2. (B)PTRSQ
3. (C)TRPQS
4. (D)QTPRS

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2¹⁴. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.

The size of the physical address space of a processor is 2ᴾ bytes. The word length is 2ᵂ bytes. The capacity of cache memory is 2ᴺ bytes. The size of each cache block is 2ᴹ words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

1. (A)P - N - log₂K
2. (B)P - N + log₂K
3. (C)P - N - M - W - log₂K
4. (D)P - N - M - W + log₂K

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is ______.

A processor has 16 integer registers (R0, R1, ..., R15) and 64 floating point registers (F0, F1, ..., F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F). The maximum value of N is __________.

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ________ bits.

The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ________.

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ________ percent.

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is ______.

Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units U_F and U_G, respectively. Given two instances of U_F and two instances of U_G, it is required to implement the computation F(G(Xᵢ)) for 1 ≤ i ≤ 10. Ignoring all other delays, the minimum time required to complete this computation is ______ nanoseconds.

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is ______.

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ______ bits.

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies τ₁, τ₂, and τ₃ such that τ₁ = 3τ₂/4 = 2τ₃. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ______ GHz, ignoring delays in the pipeline registers.

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. Which processor has the highest peak clock frequency?

1. (A)P1
2. (B)P2
3. (C)P3
4. (D)P4

An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________.

The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is __________.